Design of 125-Level Asymmetrical Multilevel Inverter with Reduced Switch Count

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N V Vinay Kumar
Gowri Manohar

Abstract

This paper provides a unique reduced component-count-efficient topology for 125-level asymmetrical multilevel inverter. The proposed design uses asymmetric DC sources and an H-bridge to produce an output voltage that can reach a maximum of 125 levels. The design and development of a multi-level inverter with a stacked half-bridge architecture that generates a 125-level output with excellent power quality is the object of the current research. The MOSFETs are triggered using a fundamental frequency switching technique that has been modified for output voltage level control. At its output, the level production circuit exclusively generates positive levels. Look-up tables are employed to regulate MOSFETs, and an H-bridge circuit is used to create polarities. 125 levels of output result in a nearly sinusoidal voltage waveform, which will give a nearly sinusoidal voltage waveform without the use of filters. The proposed work is Simulated in MATLAB/Simulink software.

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How to Cite
[1]
N V Vinay Kumar and Gowri Manohar, “Design of 125-Level Asymmetrical Multilevel Inverter with Reduced Switch Count”, IJSCE, vol. 14, no. 3, pp. 1–5, Jul. 2024, doi: 10.35940/ijsce.H9914.14030724.
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How to Cite

[1]
N V Vinay Kumar and Gowri Manohar, “Design of 125-Level Asymmetrical Multilevel Inverter with Reduced Switch Count”, IJSCE, vol. 14, no. 3, pp. 1–5, Jul. 2024, doi: 10.35940/ijsce.H9914.14030724.

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