Design of 125-Level Asymmetrical Multilevel Inverter with Reduced Switch Count
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Abstract
This paper provides a unique reduced component-count-efficient topology for 125-level asymmetrical multilevel inverter. The proposed design uses asymmetric DC sources and an H-bridge to produce an output voltage that can reach a maximum of 125 levels. The design and development of a multi-level inverter with a stacked half-bridge architecture that generates a 125-level output with excellent power quality is the object of the current research. The MOSFETs are triggered using a fundamental frequency switching technique that has been modified for output voltage level control. At its output, the level production circuit exclusively generates positive levels. Look-up tables are employed to regulate MOSFETs, and an H-bridge circuit is used to create polarities. 125 levels of output result in a nearly sinusoidal voltage waveform, which will give a nearly sinusoidal voltage waveform without the use of filters. The proposed work is Simulated in MATLAB/Simulink software.
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Trabelsi, M., Vahedi, H., & Abu-Rub, H. (2021). Review on single-DC-source multilevel inverters: Topologies, challenges, industrial applications, and recommendations. IEEE Open Journal of the Industrial Electronics Society, 2, 112-127. https://doi.org/10.1109/OJIES.2021.3054666
Vemuganti, H. P., Sreenivasarao, D., Ganjikunta, S. K., Suryawanshi, H. M., & Abu-Rub, H. (2021). A survey on reduced switch count multilevel inverters. IEEE Open Journal of the Industrial Electronics Society, 2, 80-111. http://dx.doi.org/10.1109/OJIES.2021.3050214
Chethan, M., & Kuppan, R. (2024). A review of FACTS device implementation in power systems using optimization techniques. Journal of Engineering and Applied Science, 71(1), 18.https://doi.org/10.1186/s44147-023-00312-7
Vijeh, M., Rezanejad, M., Samadaei, E., & Bertilsson, K. (2019). A general review of multilevel inverters based on main submodules: Structural point of view. IEEE Transactions on Power Electronics, 34(10), 9479-9502. http://dx.doi.org/10.1109/TPEL.2018.2890649
K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain (2016), “Multilevel Inverter Topologies with Reduced Device Count: a Review”, IEEE Transactions on Power Electronics, vol. 31, no. 1, pp. 135–151. https://doi.org/10.1109/TPEL.2015.2405012
NV, V. K. (2023). A comprehensive survey on reduced switch count multilevel inverter topologies and modulation techniques. Journal of Electrical Systems and Information Technology, 10(1), 3. https://doi.org/10.1186/s43067-023-00071-8
R. Agrawal and S. Jain (2017), “Comparison of Reduced Part Count Multilevel Inverters (RPC-MLIs) for Grid Interfacing”, IETE Journal of Research, pp. 1–14. https://doi.org/10.1080/03772063.2017.1367262
Venkataramanaiah, Y. Suresh, and A. K. Panda (2017), “A Review on Symmetric, Asymmetric”, Renewable Sustainable Energy Reviews, vol. 76, pp. 788–812. https://doi.org/10.1016/j.rser.2017.03.066
N. V. Vinay Kumar and Tenepalli Gowri Manohar (2024), “Meta Heuristic Algorithm Based Novel Dstatcom Architecture for Power Quality Improvement”. International Journal of Experimental Research and Review, 38, 119-131. https://doi.org/10.52756/ijerr.2024.v38.011
Marif Daula Siddique, Saad Mekhilef, Noraisyah Mohamed Shah, Adil Sarwar, Mohammad Tayyab(2019), “Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count”, IEEE Access, vol 7, pp 86374-86383 https://doi.org/10.1109/ACCESS.2019.2925277
Juárez-Abad, J.A.,Barahona-Avalos, J.L., Linares-Flores, J.: PWM techniques for an asymmetric multilevel binary inverter: an FPGA-based implementation. IET Power Electron.14, 1529–1539 (2021). https://doi.org/10.1049/pel2.12131
M.E, M. R., & Sudha, K. R. (2019). Asymmetrical Cascade Multilevel Inverter Design using Modified Level Shift Pulse Width Modulation. In International Journal of Recent Technology and Engineering (IJRTE) (Vol. 8, Issue 2, pp. 2650–2659). https://doi.org/10.35940/ijrte.b1843.078219
R, A., D, V., S, M., M, R., & A, K. (2019). Performance Examination of SEPIC Based Hybrid Cascaded Single-Phase Multilevel Inverter. In International Journal of Engineering and Advanced Technology (Vol. 9, Issue 2, pp. 3644–3648). https://doi.org/10.35940/ijeat.b2288.129219
Wani, G. H., & Shedge, Dr. D. K. (2019). Design and Development of Microcontroller Based Multilevel Inverter. In International Journal of Innovative Technology and Exploring Engineering (Vol. 8, Issue 10, pp. 1775–1778). https://doi.org/10.35940/ijitee.i8599.0881019
Karpe, Dr. S. R., Deokar, S., & Shinde, Dr. U. B. (2024). Predictive Controller Strategies for Electrical Drives System using Inverter System. In International Journal of Emerging Science and Engineering (Vol. 12, Issue 7, pp. 27–39). https://doi.org/10.35940/ijese.e4114.12070624
O. S., A., B. M, Y., & O, O. (2023). Scientific Assessment of Locally and Factory Built 2 KVA Modified Sine Wave Solar Powered Inverters. In Indian Journal of Microprocessors and Microcontroller (Vol. 3, Issue 1, pp. 1–12). https://doi.org/10.54105/ijmm.d4057.033123