Performance Analysis of an Efficient Router using X Y Algorithm

Abstract

As more and more functions are expected to be performed by a single electronic device (such as a smartphone, smart television, etc.), the need to have more and more components on SoC is increasing, posing new difficulties for NoC. The majority of NoC designs utilise mesh, torus, or other topologies to ensure a robust router. Most solutions, however, fall short when it comes to addressing key issues like throughput, area overhead, and latency, as well as QoS and congestion. The current paper proposes a concept for a reconfigurable router that can be used in No C settings. For the suggested router’s design, we use Verilog, formal language for describing hardware (Verilog HDL). The four-channel router presented here has an east-west-north-south orientation and a crossbar switch connecting the two pairs of channels. Each channel consists of a multiplexer and a FIFO buffer. The input and output are handled by multiplexers, and the data is stored in FIFO buffers. The FIFO and multiplexer architectures for the south channel are developed initially. Afterwards the remaining three channels and the crossbar switch are made. Routers use channels, FIFO buffers, multiplexers, and crossbar switches in their overall design. Simulating the proposed design in Model sim and obtaining the RTL view in Xilinx ISE 14.0 are the two primary methods of approaching this problem. The suggested reconfigurable router’s power consumption is greatly reduced by employing the Power gating technique.. The XPower Analyzer application is used to determine the total power. As demonstrated by the findings obtained, the proposed design uses less energy than conventional reconfigurable routers.