An Efficient AES Design and Implementation Using FPGA
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The more technology develops, the greater the amount of digital information. This requires that information be secure and free from hacking, so we use encryption algorithms. One of the most famous is the Advanced Encryption Standard (AES). This paper deals with the hardware implementation of the AES Rijndael Encryption Algorithm using Xilinx Virtex-6 & Artix-7 FPGA. The work aims for a balanced design between speed, area, and power. The S-Box hardware design is based on pre-calculated look-up tables (LUTs). This method is characterized by less time and less architectural complexity. The mix-column transformations are calculated by shift and XOR methods. The encryption block is efficiently designed using Verilog-HDL and synthesized on a Virtex-6 chip (Target Device) with the help of Xilinx ISE Design Suite 14.7 Tool. The proposed architecture has good results regarding throughput, area, and power.
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